module adder_32bit(Sum,A,B);
	input [31:0] A,B;
	output [32:0] Sum;
	wire C1,C2,C3,C4,C5,C6,C7;

		adder_4bit A1 (C1,Sum[3:0],A[3:0],B[3:0],1'b0);
		adder_4bit A2 (C2,Sum[7:4],A[7:4],B[7:4],C1);
		adder_4bit A3 (C3,Sum[11:8],A[11:8],B[11:8],C2);
		adder_4bit A4 (C4,Sum[15:12],A[15:12],B[15:12],C3);
		adder_4bit A5 (C5,Sum[19:16],A[19:16],B[19:16],C4);
		adder_4bit A6 (C6,Sum[23:20],A[23:20],B[23:20],C5);
		adder_4bit A7 (C7,Sum[27:24],A[27:24],B[27:24],C6);
		adder_4bit A8 (Sum[32],Sum[31:28],A[31:28],B[31:28],C7);
endmodule

module adder_4bit(Cout,Sum,A,B,Cin);
	input [3:0] A,B;
	input Cin;
	output [3:0] Sum;
	output Cout;

	wire C1,C2,C3,C4;

		full_adder U1 (C1,Sum[0],A[0],B[0],Cin);
		full_adder U2 (C2,Sum[1],A[1],B[1],C1);
		full_adder U3 (C3,Sum[2],A[2],B[2],C2);
		full_adder U4 (Cout,Sum[3],A[3],B[3],C3);
endmodule

module full_adder(C,S,A,B,Cin);
	input A,B,Cin;
	output C,S;
	wire ab,ca,bc;

	xor(S,A,B,Cin);
	and(ab,A,B);
	and(ca,A,Cin);
	and(bc,B,Cin);
	or(C,ab,ca,bc);

endmodule

/*module test_32b();               test bench module for first_module() 
    reg[31:0]    A, B;
    wire[32:0]   Sum;

    adder_32bit ba(Sum,A,B);

    initial begin
        $monitor ($time,"\ta=%d\tb=%d\tSum=%d",A,B,Sum);
        A = 32'd0; B = 32'd0; 
		#1 A = 32'd3; B = 32'd4; 
		#1 A = 32'd40; B = 32'd50;
		#1 A = 32'd1000; B= 32'd2000;
		#1 A = 32'd320; B=32'd500;
        #1 $finish;
    end
endmodule*/
